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Freescale MCF51AG128三相BLDC马达控制设计方案

2017-01-21 13:17:01      点击次数:274
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– Additional external watchdog monitor (EWM) to helpreset external circuits
– Low-voltage detection with reset or interrupt
– Separate low voltage warning with selectable trip points
– Illegal opcode and illegal address detection with reset
– Flash block protection for each array to preventaccidental write/erasure
– Hardware CRC module to support fast cyclicredundancy checks
• Debug Support
– Single-wire back ground debug interface
– Real-time debug support, with six hardware breakpoints(4 PC, 1 address pair and 1 data) that can be configuredinto a 1- or 2-level trigger
– On-chip trace buffer provides programmable start/stoprecording conditions
– Support for real-time program (and optional partial data)trace using the debug visibility bus
• DMA Controller
– Four independently programmable DMA channelsprovide the means to directly transfer data betweensystem memory and I/O peripherals
– DMA enabled peripherals include IIC, SCI, SPI, FTM,HSCMP, ADC, RTC, and eGPIO, and the DMA requestfrom these peripherals can be configured as DMAsource or as an iEvent input
• CF1_INTC
– Support of 44 peripheral I/O interrupt requests and sevensoftware (one per level) interrupt requests
– Fixed association between interrupt request source, leveland priority, up to two requests can be remapped to thehighest maskable level and priority
– Unique vector number for each interrupt source
– Support for service routine interrupt acknowledge(software IACK) read cycles for improved system
performance
– Ability to mask any individual or all interrupt sources
• System Clock Sources
– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1MHz to 16 MHz
– Internal Clock Source (ICS) — Frequency-locked-loop (FLL) controlled by internal or external eference; trimmableinternal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 ºC)大电流电感
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