Freescale MCF51AG128三相BLDC马达控制设计方案
2017-01-21 13:17:01 点击次数：
上一篇：应用于小封装充电器的低成本适配器解决方案 贴片电感
• Peripherals
– ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single orcontinuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversioncomplete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation;selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardwaretriggers during ping-pong mode; on-chip temperature sensor
– PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signalinitiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORedtogether; pulsed output could be used for HSCMP windowing signal
– iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use asinterrupt requests, DMA transfer requests, or hardware triggers
– FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for eachcomplementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs orindependent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which havewrite buffer can be synchronized; write protection for critical registers; backwards compatible with TPM
– TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, outputcompare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt
– CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16 + x12+ x5 + 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value
– HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparatoroutput; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltagereference from two internal DACs; support DMA transfer大电流电感详解六种逆变电源的控制算法 FB脚的电压随输出功率的增加而增加的原因 多种增值功能的手持POS机设计方案 五大要素助你选择快速连接器 “一点接地”布局实现PSR电源设计之EMC设计技巧 龙门吊大车电机过载原因分析及解决方案 废水资源化处理过程在线监测方法 怎样选择最优的 Buck 转换器拓扑？ 工业通信中的检错码技术 [DCDC]电机电路总是电流过大，烧保险丝，请各位帮忙
• Peripherals
– ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single orcontinuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversioncomplete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation;selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardwaretriggers during ping-pong mode; on-chip temperature sensor
– PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signalinitiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORedtogether; pulsed output could be used for HSCMP windowing signal
– iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use asinterrupt requests, DMA transfer requests, or hardware triggers
– FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for eachcomplementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs orindependent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which havewrite buffer can be synchronized; write protection for critical registers; backwards compatible with TPM
– TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, outputcompare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt
– CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16 + x12+ x5 + 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value
– HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparatoroutput; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltagereference from two internal DACs; support DMA transfer大电流电感
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